中圖分類號：TN915.05 文獻標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.256678
中文引用格式： 劉寶琴，羅向征，林茂，等. 智能網(wǎng)卡加速Ceph存儲的性能研究[J]. 電子技術(shù)應(yīng)用，2025，51(12)：14-19.
英文引用格式： Liu Baoqin，Luo Xiangzheng，Lin Mao，et al. Research on accelerating Ceph storage performance with SmartNICs[J]. Application of Electronic Technique，2025，51(12)：14-19.

Research on accelerating Ceph storage performance with SmartNICs

Abstract： This paper focuses on the issue of limited multi-core parallel scalability caused by thread lock contention mechanisms in the architecture of the Ceph storage system's Object Storage Device (OSD). It conducts research on collaborative optimization technologies between the next-generation Crimson-OSD architecture and SmartNICs, proposing a hierarchical cooperative optimization framework. Related studies demonstrate that employing SmartNIC-based cooperative optimization achieves a 70% reduction in CPU utilization through RDMA network offloading, while heterogeneous computing engines enable hardware acceleration for erasure coding, improving data recovery speed by 4.84 times. The research outcomes provide theoretical foundations and key technical references for hardware acceleration in distributed storage systems, offering guidance for optimizing storage systems in data-intensive scenarios such as high-performance computing and cloud-edge-end integration.

Key words : SmartNIC；Ceph storage system；performance optimization；hardware acceleration；distributed storage system